AMD Zen 6 could bring 24-core Ryzen CPUs and 144 MB of cache to gaming Ryzen X3D
AMD's upcoming Zen 6 architecture could give future Ryzen processors a significant boost in core count and cache capacity. The new design supports up to 12 cores per chiplet, which could pave the way not only for 24-core desktop Ryzen CPUs but also for new Ryzen X3D gaming processors with more cores and larger caches.
AMD revealed new details about Zen 6 during a technical presentation on its upcoming Epyc Venice server processors. Although the company has yet to announce consumer Ryzen chips based on the architecture, both product families share the same underlying CPU design.
Zen 6 packs 12 full-performance cores and 48 MB of shared L3 cache into a core complex die, or CCD. That represents a 50 % increase in both core count and cache compared with Zen 5, which has eight cores and 32 MB of L3 cache per chiplet. The amount of cache per core remains unchanged at 4 MB.
This could be particularly useful for gaming. Current 12-core Ryzen processors need two chiplets. Communication between separate CCDs introduces additional latency, especially in games that distribute their workloads across both. With Zen 6, AMD could build a 12-core processor using a single chiplet, allowing all cores to share the same L3 cache.
The new architecture could also simplify future Ryzen X3D processors. AMD's current dual-chiplet X3D models need additional scheduling logic to direct games toward cores with access to the extra 3D V-Cache. A single 12-core chiplet with a large shared cache could eliminate much of that complexity.
AMD has already demonstrated a similar configuration with its Epyc Venice-X server processors. The design combines 48 MB of built-in L3 cache with 96 MB of stacked 3D V-Cache, for a total of 144 MB per 12-core chiplet. For comparison, current X3D processors offer 96 MB of total L3 cache per CCD.
Zen 6 also brings architectural improvements beyond additional cores and cache. AMD says the new design features better branch prediction and faster recovery from incorrect predictions. The operation cache has also grown to roughly 6,750 entries, while the front end can deliver up to 18 operations per cycle. These changes are intended to improve instructions per clock (IPC), which could benefit gaming performance even in titles that do not make full use of 12 cores.
AMD's technical presentation showed approximately 27 % higher geometric-mean IPC for the denser Zen 6c variant across AI and server workloads. However, this figure does not represent gaming performance or the standard Zen 6 cores, so it should not be treated as a direct measure of future Ryzen improvements.
There is still a lot we don't know about consumer Zen 6 processors, including their clock speeds, power consumption and final configurations. Nevertheless, the architecture gives AMD an opportunity to combine the gaming advantages of its eight-core X3D processors with the additional cores and cache capacity of its Ryzen 9 lineup.
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